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| Advance Information MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by DSP56166/D DSP56166 Ceramic Quad Flat Pack (CQFP) Available in a 112 pin, small footprint, surface mount package. 16-bit General Purpose Digital Signal Processor The DSP56166 is the second member of Motorola's DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in codec and phase locked loop (PLL). This MPU-style DSP also contains, memories, digital peripherals, and provides a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCETM) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly simplified by using the OnCE. The DSP56166 RAM based is an off the shelf part since there are no user programmable ROM's onchip. The DSP56166 ROM based contains a 12K ROM (8Kx 16 program ROM and 4Kx16 data ROM). The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools of the DSP56100 family, DSP56000 family, and DSP96002 are so similar that learning to design and program one greatly reduces the time needed to learn the others. DSP56166ROM Feature List DSP56100 Family Features * Up to 30 Million Instructions per Second (MIPS) at 60 MHz.- 33.3 ns Instruction cycle * Single-cycle 16 x 16-bit parallel Multiply-Accumulate * 2 x 40-bit accumulators with extension byte * Fractional and integer arithmetic with support for multiprecision arithmetic * Highly parallel instruction set with unique DSP addressing modes * Nested hardware DO loops including infinite loops and DO zero loop * Two instruction LMS adaptive filter loop * Fast auto-return interrupts * Three external interrupt request pins * Three 16-bit internal data and three 16-bit internal address buses * Individual programmable wait states on the external bus for program, data, and peripheral memory spaces * Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin * On-chip memory-mapped peripheral registers * Low Power Wait and Stop modes * On-Chip Emulation (OnCE) for unobtrusive, processor speed independent debugging * Operating frequency down to DC * 5V single power supply * Low power (HCMOS) DSP56166ROM On-chip Resources * * * * * * * 4K x 16 on-chip data RAM 4K x 16 on-chip data ROM 256 x 16 on-chip program RAM 8K x 16 on-chip program ROM One external 16-bit address bus One external 16-bit data bus On-chip voice band codec (A/D-D/A) - Internal voltage reference (2/5 of positive power supply) - No off-chip components required 25 general purpose I/O pins On-chip, programmable PLL Byte-wide Host Interface with DMA support Two independent reduced synchronous serial interfaces * One 16-bit timer * 112 pin quad flat pack packaging * * * * Operational Differences Of The ROM Based Part From The RAM Based Part * XROM can only be accessed during a single read or the first read of a dual parallel read instruction (see note on page 2) * Reset mode 1 vectors to P:$0100 * PROM area P:$2080 -- P:$20FF is reserved and should not be programmed or accessed by the user This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA (c)MOTOROLA INC., 1993 6/15/93 XAB1 XAB2 PORT B OR HOST ADDRESS GENERATION UNIT PAB EXTERNAL ADDRESS BUS SWITCH ADDRESS 16 PORT A 15 7+10 ON-CHIP PERIPHERALS HOST, RSSI0, RSSI1, TIMER GPI/O, CODEC BOOTSTRAP ROM 64x16 PROGRAM RAM 2Kx16 DATA RAM 4Kx16 BUS CONTROL 10 CODEC, PORT C AND/OR RSSI0, RSSI1, TIMER XDB INTERNAL DATA BUS SWITCH AND BIT MANIPULATION UNIT PDB GDB EXTERNAL DATA BUS SWITCH 16 DATA EXTAL SXFC CLKO CLOCK AND PLL PROGRAM CONTROL UNIT PROGRAM ADDRESS GENERATOR PROGRAM DECODE CONTROLLER PROGRAM INTERRUPT CONTROLLER DATA ALU 16x16+40 - 40-BIT MAC TWO 40-BIT ACCUMULATORS OnCE 4 RESET MODA/IRQA MODB/IRQB MODC/IRQC 16 BITS Figure 1 DSP56166 Block Diagram In the USA: For technical assistance call: DSP Applications Helpline (512) 891-3230 For availability and literature call your local Motorola Sales Office or Authorized Distributor. For free application software and information call the Dr. BuB electronic bulletin board: 9600/4800/2400/1200/300 baud (512) 891-3771 (8 data bits, no parity, 1 stop) In Europe, Japan and Asia Pacific Contact your regional sales office or Motorola distributor. Note: For the ROM part only (DSP56166ROM) -- Since the on-chip XROM is only connected to the XAB1 address bus, the data located in this ROM is only accessible by the first read of a single read instruction or the first read of a dual parallel read instruction. Therefore, during development using the RAM based part, the data to be mapped in the on-chip XROM on the ROM based part should not be accessed with a second read during a dual parallel read instruction. 2 DSP56166 Technical Data Sheet MOTOROLA INTRODUCTION This data sheet is intended to be used with the DSP56100 Family Manual and the DSP56166 User's Manual. The DSP56100 Family Manual provides a description of the components of the DSP5616 core processor that are common to all DSP56100 family processors and includes a detailed description of the basic DSP56100 family instruction set. The DSP56166 User's Manual provides a description of the memory and peripherals that are specific to the DSP56166. The DSP56166 Data Sheet provides electrical specifications and timings that are specific to the DSP56166. The DSP56166 pinout is shown in Figure 3. The input and output signals on the chip are organized into the 13 functional groups shown in Table 1. A15 address lines. PS/DS is high for program memory access and is low for data memory access. If the external bus is not used during an instruction cycle (t0,t1,t2,t3), PS/DS goes high in t0. PS/DS is in the high impedance state during hardware reset, stop mode and when the DSP is not the bus master. PEREN (Peripheral Enable) -- three state active low output. This output is asserted only when external peripheral space of the data memory is referenced (any address between X:$FF00 and X:$FF7F). PEREN timing is the same as the A0-A15 address lines; it is asserted and deasserted during t0. PEREN is high for any program memory access and for data memory access not in the space X:$FF00 - X:$FF7F. PEREN is in the high impedance state during hardware reset, stop mode and when the DSP is not the bus master. R/W (Read/Write)- three state, active low output. Timing is the same as for the address lines, providing an "early write" signal. R/W (which changes in t0) is high for a read access and is low for a write access. If the external bus is not used during an instruction cycle (t0,t1,t2,t3), R/W goes high in t0. R/W is three-stated during hardware reset, stop mode and when the DSP is not the bus master. Table 1 Functional Group Pin Allocations Functional Group Address and Data Buses Bus Control Interrupt and Mode Control Clock and PLL Host Interface or PIO Timer Interface or PIO RSSI Interfaces or PIO On-chip CODEC On-chip emulation (OnCE) Power (Vdd) Ground (Vss) APower (Vdda) AGround (Vssa) Total Number of Pins 32 10 4 3 15 2 8 7 4 9 16 1 1 112 WR (Write Enable) -- three state, active low output. This output is asserted during external memory write cycles. When WR is asserted in t1, the data bus pins D0-D15 become outputs and the DSP puts data on the bus during the leading edge of t2. When WR is deasserted in t3, the external data has been latched inside the external device. When WR is asserted, it qualifies the A0-A15 and PS/DS pins. WR can be connected directly to the WE pin of a static RAM. WR is three-stated during hardware reset, stop mode and when the DSP is not the bus master. (Read Enable) -- three state, active low output. This output is asserted during external memory read cycles. When RD is asserted in late t0/early t1, the data bus pins D0-D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted in t3, the external data has been latched inside the DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins. RD can be connected directly to the OE pin of a static RAM or ROM. RD is three-stated during hardware reset, stop mode and when the DSP is not the bus master. (Bus Strobe) -- active low output. Asserted at the start of a bus cycle (during t0) and deasserted at the end of the bus cycle (during t2). This pin provides an "early bus start" signal which can be used as address latch and as an "early bus end" signal which can be used by an external bus controller. BS is three-stated during hardware reset, stop mode and when the DSP is not the bus master. (Transfer Acknowledge) -- active low input. If there is no external bus activity, the TA input is ignored by the DSP. When there is external bus cycle activity, TA can be used to insert wait states in the external bus cycle. TA is sampled on the leading edge of the clock. Any number of wait states from 1 to infinity may be inserted by using TA. If TA is sampled high on the leading edge of the clock beginning the bus cycle, the bus cycle will end 2T after the TA has been sampled low on a leading edge of the clock; if the Bus Control Register (BCR) value does not program more wait RD ADDRESS AND DATA BUS (32 PINS A0-A15 (Address Bus) -- three state, active high outputs. A0A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0A15 are three-stated during hardware reset, stop mode and when the DSP is not the bus master. D0-D15 (Data Bus) -- three state, active high, bidirectional input/outputs. Read data is sampled on the trailing edge of t2, while write data output is enabled by the leading edge of t2 and three-stated at the leading edge of t0. If there is no external bus activity, D0-D15 are three-stated. D0-D15 are also three-stated during hardware reset. BS TA BUS CONTROL (10 PINS) PS/DS (Program /Data Memory Select) -- three state active low output. This output is asserted only when external data memory is referenced. PS/DS timing is the same for the A0- DSP56166 PRELIMINARY MOTOROLA 3 T0 T1 T2 T3 T0 T1 T2 T3 T0 CLKO BS A0-A15 PS/DS R/W WR RD D0-D15 Data In Bus Operation (Read-Write- 0WT) T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw Data Out T2 Tw T2 Tw T2 T3 T0 T1 CLKO BS PS/DS A0-A15 R/W WR RD D0-D15 Data in Data out Bus Operation (Read-Write- 3WT) Figure 2 Bus Operation MOTOROLA 4 PRELIMINARY DSP56166 Interrupt and Mode Control PB0-PB7 H0-H7 HA0 HA1 HA2 HR/W HEN HREQ HACK 1 1 MODA/IRQA MODB/IRQB MODC/IRQC RESET Clock and PLL PB8 PB9 PB10 PB11 PB12 PB13 PB14 Host Parallel Interface EXTAL CLKO SXFC VddS GNDS External Bus 56 pins (42 func. 5Vdd;9Vss) A0-A15 D0-D15 Vdd Add/Data Vss Add/Data BS PS/DS PEREN WR RD R/W TA BR BG BB Vdd Control Vss Control DSI/OS0 DSCK/OS1 DSO DR Quiet Vdd Vss DSP56166 4 8 PC0 PC1 PC2 Vdd Port B Vss Port B STD0 SRD0 SCK0 SFS0 STD1 SRD1 SCK1 SFS1 TIN TOUT Mic Aux Timer Two Serial Interfaces PORT A PC4 PC5 PC6 PC7 PC9 1 1 PC10 PC11 On-chip Emulation 2 2 112 pins (85 functional pins 16 ground pins 9 power pins 1 Aground pins 1 Apower pin) SPKP SPKM Vrad Vrda Vdiv VddA VssA Vdd port C Vss Port C On-chip Codec 1 1 1 2 Figure 3 DSP56166 Pinout DSP56166 PRELIMINARY MOTOROLA 5 T0 T1 T2 T3 T0 T1 T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 CLKO TA BS T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 T3 T0 T1 T2 CLKO TA BS Figure 4 TA Controlled Accesses states. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. TA is still sampled during the leading edge of the clock when wait states are controlled by the BCR value. In that case, TA will have to be sampled low during the leading edge of the last period of the bus cycle programmed by the BCR (2T before the end of the bus cycle programmed by the BCR) in order not to add any wait states. TA should always be deasserted during t3 to be sampled high by the leading edge of T0. If TA is sampled low (asserted) at the leading edge of the t0 beginning the bus cycle, and if no wait states are specified in the BCR register, zero wait states will be inserted in the external bus cycle, regardless the status of TA during the leading edge of T2. BR (Bus Request) -- active low output when in master mode, active low input when in slave mode. This pin is an input (slave mode) after reset with MODC pin low or when the bus arbitration mode bit in the OMR register is cleared. In this mode, the bus request BR allows another device such as a processor or DMA controller to become the master of the DSP external data bus D0-D15 and external address bus A0-A15. The DSP asserts BG a few T states after the BR input is asserted. The DSP bus controller will release control of the external data bus D0-D15, address bus A0-A15 and bus control pins PS/ DS, BS, RD, WR, R/W and PEREN at the earliest time possible consistent with proper synchronization. These pins will then be placed in the high impedance state and the BB pin will be deasserted. The DSP will continue executing instructions only if internal program and data memory resources are being accessed. If the DSP requests the external bus while BR input pin is asserted, the DSP bus controller inserts wait states until the external bus becomes available (BR and BB deasserted). Note that interrupts are not serviced when a DSP instruction is waiting for the bus controller. Note also that BR is prevented from interrupting the execution of a read/ modify/ write instruction. This pin becomes an output (Master Mode) after reset with MODC pin high or when the bus arbitration mode bit in the OMR register is set. In this mode, the DSP is not the external bus master and has to assert BR to request the bus mastership. The DSP bus controller will insert wait states until BG input is asserted and will then begin normal bus accesses after the rising of the clock which sampled BB high. The BR output signal will remain asserted until the DSP no longer needs the bus. In this mode, the Request Hold bit (RH) of the Bus Control Register (BCR) allows BR to be asserted under software control. During external accesses caused by an instruction executed out of external program memory, BR remains asserted low for consecutive external memory accesses. In the master mode, BR can also be used for non arbitration purpose: if BG is always asserted, BR is asserted in t0 of every external bus access. It can then be used as a chip select to turn a external memory device off and on between internal and external bus accesses. BR timing is in that case similar to A0-A15, R/W and PS/DS; it is asserted and deasserted during t0. BG (Bus Grant) -- active low input when in master mode, active low output when in slave mode. Output after power on reset if the slave mode is selected, this pin is asserted to acknowledge an external bus request. It indicates that the DSP will release control of the external address bus A0A15, data bus D0-D15 and bus control pins when BB is deasserted. The BG output is asserted in response to a BR input. When the BG output is asserted, BB will be deasserted and the external address bus A0-A15, data bus D0-D15 and bus control pins will be in the high impedance state at the end of the current instruction. BG assertion may occur in the middle of an instruction which requires more than one external bus cycle for execution. Note that BG assertion will not occur during indivisible read-modify-write instructions (BFSET, BFCLR, BFCHG). When BR is deasserted, the BG output is deasserted and the DSP MOTOROLA 6 PRELIMINARY DSP56166 regains control of the external address bus, data bus, and bus control pins until the BB pin is sampled high. This pin becomes an input if the bus arbitration mode bit in the OMR register is set (Master Mode). It is asserted by an external processor when the DSP may become the bus master. The DSP can start normal external memory access after the BB pin has been deasserted by the previous bus master. When BG is deasserted, the DSP will release the bus as soon as the current transfer is completed. The state of BG may be tested by testing the BS bit in the Bus Control Register. BG is ignored during hardware reset. BB (Bus Busy) -- active low input when not bus master, active low output when bus master. This pin is asserted by the DSP when it becomes the bus master and it performs an external access. It is deasserted when the DSP releases bus mastership. BB becomes an input when the DSP is no longer the bus master. mode can be changed by software writing the MC bit of the OMR register. Several clock cycles after leaving the RESET state, the MODC pin changes to the external interrupt request IRQC. The IRQC input is an external interrupt request which indicates that an external device is requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. RESET (Reset) -- This input is a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the reset pin is deasserted, the initial chip operating mode is latched from the MODA and MODB pins. The internal reset signal is deasserted synchronously with the internal clocks. POWER, GROUND, AND CLOCK (28 PINS) VDD (8) (Power) -- power pins. VSS (15) (Ground) -- ground pins. VDDS (Synthesizer Power) -- This pin supplies a quiet power source to the PLL to provide greater frequency stability. GNDS (Synthesizer Ground) -- This pin supplies a quiet ground source to the PLL to provide greater frequency stability. VDDA (Power Supply input) -- This pin is the positive analog supply input. It should be connected to VCC when the codec is not used. VSSA (Analog Ground) -- This pin is the analog ground return. It should be connected to VSS when the codec is not used. EXTAL (External Clock/Crystal Input) -- This input should be connected to an external clock or to an external oscillator. A sine wave with a minimum swing of 1Vpp can be applied to this pin. After being squared, the input frequency can be used as the DSP core internal clock. In that case, it is divided by two to produce a four phase instruction cycle clock, the minimum instruction time being two input clock periods.This input frequency is also used, after division, as input clock for the on-chip codec and the on-chip phase locked loop (PLL). CLKO (Clock Output) -- This pin outputs a buffered clock signal. By programming two bits (CS1-CS0) inside the PLL Control Register (PLCR), the user can select between outputting a squared version of the signal applied to EXTAL, a squared version of the signal applied to EXTAL divided by 2, and a delayed version of the DSP core master clock. The clock frequency on this pin can be disabled by setting the Clockout Disable bit (CD; bit 7) of the Operating Mode Register (OMR). In this case, the pin is driven low and can be left floating. SXFC (External Filter Capacitor) -- This pin is used to add an external capacitor to the PLL filter circuit. A low leakage capacitor should be connected between SXFC and VDDS; it should be located very close to those pins. INTERRUPT AND MODE CONTROL (4 PINS) MODA/IRQA (Mode Select A/External Interrupt Request A) -- This input has two functions - to select the initial chip operating mode and, after synchronization, to allow an external device to request a DSP interrupt. MODA is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODA pin changes to the external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request which indicates that an external device is requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state. MODB/IRQB (Mode Select B/External Interrupt Request B) -- This input has two functions - to select the initial chip operating mode and, after internal synchronization, to allow an external device to request a DSP interrupt. MODB is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODB pin changes to the external interrupt request IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request which indicates that an external device is requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. MODC/IRQC (Mode Select C/External Interrupt Request C) -- This input has two functions - to select the initial bus operating mode and after internal synchronization, to allow an external device to request a DSP interrupt. MODC is read and internally latched in the DSP when the processor exits the RESET state.When tied high, the external bus is programmed in the master mode (BR output and BG input) and when tied low the bus is programmed in the slave mode (BR input and BG output). After RESET, the bus operating DSP56166 PRELIMINARY MOTOROLA 7 HOST INTERFACE (15 PINS) H0-H7 (Host Data Bus) -- This bidirectional data bus is used to transfer data between the host processor and the DSP. This bus is an input unless enabled by a host processor read. H0-H7 may be programmed as general purpose parallel I/O pins called PB0-PB7 when the Host Interface (HI) is not being used. HA0-2 (Host Address 0-2) -- These inputs provide the address selection for each HI register and should be stable when HEN is asserted. HA0-HA2 may be programmed as general purpose parallel I/O pins called PB8-PB10 when the HI is not being used. HR/W (Host Read/Write) -- This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W should be stable when HEN is asserted. HR/W may be programmed as a general purpose I/O pin called PB11 when the HI is not being used. HEN (Host Enable) -- This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 becomes an output and DSP data may be latched by the host processor. When HEN is asserted and HR/W is low, H0-H7 is an input and host data is latched inside the DSP when HEN is deasserted. Normally a chip select signal derived from host address decoding and an enable clock is connected to the Host Enable. HEN may be programmed as a general purpose I/O pin called PB12 when the HI is not being used. a general purpose I/O pin called PC10 when the external event function is not being used. TOUT (Timer output) -- This output generates pulses or toggles on a timer overflow event or a compare event. TOUT may be programmed as a general purpose I/O pin called PC11 when disabled by the timer out enable bits (TO2-TO0). SYNCHRONOUS SERIAL INTERFACES (RSSI0 AND RSSI1) (8 PINS) STD0/PC0 (RSSI0 Transmit Data) -- This output pin transmits serial data from the RSSI0 Transmit Shift Register. STD0 may be programmed as a general purpose I/O pin called PC0 when the RSSI0 STD0 function is not being used. SRD0/PC1 (RSSI0 Receive Data) -- This input pin receives serial data and transfers the data to the RSSI0 Receive Shift Register. SRD0 may be programmed as a general purpose I/O pin called PC1 when the RSSI0 SRD0 function is not being used. SCK0/PC2 (RSSI0 Serial Clock) -- This bidirectional pin provides the serial bit rate clock for the RSSI0 interface. The clock signal can be continuous or gated and is used by both the transmitter and receiver. SCK0 may be programmed as a general purpose I/O pin called PC2 when the RSSI0 interface is not being used. SFS0/PC4 (Serial Frame Sync 0) -- This bidirectional pin is used by the RSSI0 serial interface as frame sync I/O or flag I/O. The SFS0 is used by both the transmitter and receiver to synchronize the data transfer of the data. It can be input or output. SFS0 may be programmed as a general purpose I/O pin called PC4 when the RSSI0 is not using this pin. (Host Request) -- This open-drain output signal is HREQ used by the HI to request service from the host processor. HREQ may be connected to an interrupt request pin of a host processor, a transfer request of a DMA controller, or a control input of external circuitry. HREQ is asserted when an enabled request occurs in the HI. HREQ is deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used. HACK (Host Acknowledge) -- This input has two functions (1) to provide a Host Acknowledge signal for DMA transfers or (2) to control handshaking and to provide a Host Interrupt Acknowledge compatible with MC68000 family processors. If programmed as a Host Acknowledge signal, HACK may be used as a data strobe for HI DMA data transfers. If programmed as an MC68000 Host Interrupt Acknowledge, HACK is used to enable the HI Interrupt Vector Register (IVR) onto the Host Data Bus H0-H7 if the Host Request HREQ output is asserted. In this case, all other HI control pins are ignored and the HI state is not affected. HACK may be programmed as a general purpose I/O pin called PB14 when the HI is not being used. STD1/PC5 (RSSI1 Transmit Data) -- This output pin transmits serial data from the RSSI1 Transmit Shift Register. STD1 may be programmed as a general purpose I/O pin called PC5 when the RSSI1 STD1 function is not being used. SRD1/PC6 (RSSI1 Receive Data) -- This input pin receives serial data and transfers the data to the RSSI1 Receive Shift Register. SRD1 may be programmed as a general purpose I/O pin called PC6 when the RSSI1 SRD function is not being used. SCK1/PC7 (RSSI1 Serial Clock) -- This bidirectional pin provides the serial bit rate clock for the RSSI1 interface. The clock signal can be continuous or gated and is used by both the transmitter and receiver. SCK1 may be programmed as a general purpose I/O pin called PC7 when the RSSI1 interface is not being used. SFS1/PC9 (Serial Frame Sync 1) -- This bidirectional pin is used by the RSSI1 serial interface as frame sync I/O or flag I/O. The SFS1 is used by both the transmitter and receiver to synchronize the data transfer of the data. It can be input or output. SFS1 may be programmed as a general purpose I/O pin called PC9 when the RSSI1 is not using this pin. 16-BIT TIMER (2 PINS) TIN (Timer input) -- This input receives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. TIN may be programmed as MOTOROLA 8 PRELIMINARY DSP56166 ON-CHIP EMULATION (4 PINS) DSI/OS0 (Debug Serial Input/Chip Status 0) -- The DSI/OS0 pin, when an input, is the pin through which serial data or commands are provided to the OnCE controller. The data received on the DSI pin will be recognized only when the DSP has entered the debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSP is not in the debug mode, the DSI/OS0 pin is an output and it provides information about the chip status. It is used in conjunction with the OS1 pin. DSCK/OS1 (Debug Serial Clock/Chip Status 1) -- The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to the OnCE. The serial clock provides pulses required to shift data into and out of the OnCE serial port. Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge. When the DSP is not in the debug mode, the DSCK/OS1pin is an output and it provides information about the chip status. It is used in conjunction with the OS0 pin. DSO (Debug Serial Output) -- The debug serial output provides the data contained in one of the OnCE controller registers as specified by the last command received from the command controller. When idle, this pin is high. When the requested data is available, the DSO line will be asserted (negative true logic) for nine T cycles (more than two instruction cycles) to indicate that the serial shift register is ready to receive clocks in order to deliver the data. When the chip enters the debug mode due to an external debug request (DR), an internal software debug request (DEBUG), a hardware breakpoint occurrence or a trace/step occurrence, this line will be asserted for eight T cycles to indicate that the chip has entered the debug mode and is waiting for commands. Data is always shifted out the OnCE serial port most significant bit (MSB) first. (Debug Request Input) -- The debug request input provides a means of entering the debug mode of operation. This pin when asserted (negative true logic) will cause the DSP to finish the current instruction being executed, enter the debug mode, and wait for commands to be entered from the debug serial input line. SPKP (Speaker Positive Output) -- This pin is the positive analog output from the on-chip D/A converter. This pin should be left floating when the codec is not used. SPKM (Speaker Negative Output) -- This pin is the negative analog output from the on-chip D/A converter. This pin should be left floating when the codec is not used. VRAD (Voltage Reference Output for the A/D) -- This pin is the output of the op-amp buffer in the reference voltage generator for the A/D section. It has a value of (2/5) VDDA. This voltage is used for analog ground internal to the block.This pin should always be connected to the Ground through two capacitors, even when the codec is not used. VRDA (Voltage Reference Output for the D/A) -- This pin is the output of the op-amp buffer in the reference voltage generator for the D/A section. It has a value of (2/5) VDDA. This voltage is used for analog ground internal to the block.This pin should always be connected to the Ground through two capacitors, even when the codec is not used. VDIV (Voltage Division Output) -- This pin is the input to the op-amp buffer in the reference voltage generator. It is connected to a resistor divider network located within the codec block which provides a voltage equal to (2/5)VDDA. This pin should be connected to the ground via a capacitor when the codec is used and should be left floating when the codec is not used. DR ON-CHIP CODEC (7 PINS) AUX (Auxiliary input) -- This pin is selected as the analog input to the A/D converter when the INS bit is set in the codec control register COCR. This pin should be left floating when the codec is not used. BIAS (Bias current pin) -- This input is used to determine the bias current for the analog circuitry. Connecting a resistor between BIAS and VGNDA will program the current bias generator. This pin should be left floating when the codec is not used. MIC (Microphone input) -- This pin is selected as the analog input to the A/D converter when the INS bit is cleared in the codec control register COCR. This pin should be left floating when the codec is not used. DSP56166 PRELIMINARY MOTOROLA 9 PINOUT AND PACKAGE INFORMATION PIN 1 IDENT 112 85 1 84 MOTOROLA DSP56166 112 CQFP PACKAGE PIN-OUT TOP VIEW 28 57 29 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FUNCTION GND4 D2 D3 VDD3 D4 D5 GND5 D6 D7 D8 D9 GND6 D10 D11 VDD4 D12 D13 GND7 D14 D15 TA DR VDDA SPKP SPKM GNDA VDIV VRDA PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 56 FUNCTION MIC AUX VRAD BG QVDD0 BR BB VDD5 WR GND8 RD PS/DS BS R/W DSO DSCK/OS1 DSI/OS0 CLKO QGND0 GNDS XFC VDDS EXTAL SFS1/PC9 GND9 PEREN SCK1/PC7 H7/PB7 PIN # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FUNCTION H6/PB6 H5/PB5 VDD6 H2/PB2 H3/PB3 H4/PB4 SRD1/PC6 STD1/PC5 H1/PB1 H0/PB0 HREQ/PB13 HACK/PB14 HEN/PB12 HRW/PB11 HA2/PB10 HA1/PB9 GND10 HA0/PB8 TOUT/PC11 VDD7 TIN/PC10 SFS0/PC4 GND11 SCK0/PC2 SRD0/PC1 STD0/PC0 RESET MODA PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 FUNCTION MODB MODC A0 A1 GND0 A2 A3 VDD1 A4 A5 GND1 QVDD1 A6 A7 A8 A9 GND2 A10 VDD2 QGND1 A11 A12 A13 GND3 A14 A15 D0 D1 Internal Vcc GND QVDD0-1 QGND0-1 A0-A15 VDD1-2 GND0-3 D0-D15 VDD3-4 GND4-7 Bus control VDD5 GND8 Port B, Once, PortC VDD6,VDD7 GND9,GND10, GND11 Codec VDDA GNDA MOTOROLA 10 PRELIMINARY DSP56166 PRELIMINARY - 6/15/93 The preliminary DC/AC electrical specifications are generated from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. APPENDIX E ELECTRICAL CHARACTERISTICS AND TIMING The DSP56166 is fabricated in high density HCMOS with TTL compatible inputs and CMOS compatible outputs. Maximum Electrical Ratings (VSS = 0 Vdc) Rating Supply Voltage All Input Voltages Current Drain per Pin excluding Vdd and VSS Storage Temperature Symbol Vdd Vin I Tstg Value -0.3 to +7.0 VSS- 0.5 toVdd + 0.5 10 -55 to +150 Unit V V mA C Operating Conditions Supply Voltage Marking Speed Min VDD(V) Max Junction Temperature Tj (C) Min Max FE60 60 MHz 4.5 5.5 -40 125 1 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 Thermal Characteristics -- CQFP Package Characteristics Thermal Resistance -- Ceramic Junction to Ambient Junction to Case (estimated) Symbol JA JC Value 40 7 Rating C/W C/W Thermal Characteristics -- PQFP Package Characteristics Thermal Resistance -- Plastic Junction to Ambient Junction to Case (estimated) Symbol JA JC Value 35 13 Rating C/W C/W This device contains protective circuitry against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either Vss or Vdd). MOTOROLA DSP56166 Technical Data Sheet 2 PRELIMINARY - 6/15/93 Power Considerations The average chip junction temperature, TJ, in C can be obtained from: TJ = TA + (PD*JA) (1) Where: TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PI/O PINT = ICC*Vdd, Watts -- Chip Internal Power PI/O = Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is: PD = K/(TJ + 273 C) Solving equations (1) and (2) for K gives: K = PD*(TA + 273 C) + JA*PD (3) (2) Where K is a constant pertaining to the particular part. K can be determined from equation (2) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JA and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation: JA = JC + CA (4) JC is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so thatJA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature. Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX Microcomponent Devices", and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User--derived values for thermal resistance may differ. 3 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 Layout Practices Each DSP56166 Vdd pin should be provided with a low-impedance path to + 5 volts. Each DSP56166 Vss pin should likewise be provided with a low-impedance path to ground. The power supply pins drive six distinct groups of logic on chip. They are: Power and Ground Connections for CQFP and PQFP Vdd 33,96 92,103 4,15 36 59,76 23 Vss 47,104 89,95,101,108 1,7,12,18 38 53,73,79 26 Function Internal Logic supply pins Address bus output buffer supply pins Data bus output buffer supply pins Bus control buffer supply pins OnCE, Port B and C output buffer supply pins Codec analog supply pins Power and Ground Connections The VDD power supply should be bypassed to ground using at least six 0.01-0.1 uF bypass capacitors located either underneath the chip's socket or as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip Vdd and Vss should be kept to less than 1/2" per capacitor lead. The use of at least a four layer board is recommended, employing two inner layers as Vdd and Vss planes. All output pins on the DSP56166 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses as well as the PS/DS, BS, RD, WR, R/W, PEREN, IRQA, IRQB, and HEN pins. Maximum PC trace lengths on the order of 6" are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vdd and Vss circuits. The analog power for the VDDA pin and the analog ground for the VSSA pin should be separated from the digital VDD and ground planes. The analog power and ground planes should only be tied to the digital power and ground planes at one point where current enters and exits only at this point. The analog VDD and ground planes should not have digital signal running over them if possible. The analog VDD and ground pins should be decoupled as close to the DSP as possible. Clocks signals should not be run across many signals and should be kept away from analog power and ground signals as well as any analog signals. Refer to Analog I/O Figure 1. for more details. MOTOROLA DSP56166 Technical Data Sheet 4 PRELIMINARY - 6/15/93 Power Dissipation (Vdd = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). The DC electrical characteristics of this device are shown below. Typic al(5V) Conditions Symbol 60 MHz Unit Digital Vdd with Codec & PLL disabled Digital Vdd WAIT Mode with CODEC & PLL disabled IDD PD IDD PD 100 500 11 55 mA mW mA mW Conditions STOP Mode with PLL and CLKO disabled Digital current drawn by the PLL when active Analog Vdd with CODEC enabled Analog Vdd with CODEC disabled Symbol Typical (5V) 400 2 2 10 10 20 75 375 Unit A mW mA mW mA mW A W IDD PD IDD PD IDDA PDA IDDA PDA In order to minimize the power dissipation, all unused digital inputs pins should be tied inactive to VDD or Vss and all unused I/O pins should be tied inactive through a 10K resistor to VDD or Vss. All port A input pins and bydirectional pins must have a valid state at all time when port A is released in order to minimize power; those pins must then be pulled up or down or driven by another device. When the codec is not used, VDDA should be connected to VDD and VssA to Vss, and all codec pins should be left floating except Vref which should still be decoupled. 5 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 Analog I/O Characteristics (VddA = 5.0 Vdc +/- 10%, TJ = -40 to +125 C). The Analog I/O characteristics of this device are shown below. Characteristic Input Impedance on Mic & Auxa Input Capacitance on Mic and Aux Peak Input Voltage on the Mic/Aux Input for Full Scale Linearity (0.14dBm0b): - 6dB- MGS1-0=00 0dB- MGS1-0=01 6dB- MGS1-0=10 17dB- MGS1-0=11 Internal Input GainVariation; G=-6dB, 0dB,6dB or 17dB (0.83dB variation due to 10% variation on Vdd): Vref Output Voltage Vref Output Current DC offset between Spkout1 and Spkout2 Allowable Differential Load Capacitance on Spkout1/2(with 1k in series) Allowable Single-ended Load Capacitance on Spkout1/2(with 0.5k in series) Maximum Single-ended Signal Output Level Maximum Differential Signal Output Level Single-ended Load Resistance Differential Load Resistance R bias Internal Output Volume Control Variation VC=-20,-15,-10,-5,0,6,12,18,24,30,35 dB (0.83dB variation due to 10% variation on Vdd) Min 46 -- -- -- -- -- G-0.83 Typ 78 -- -- -- -- -- G Max 1400 10 1.414 0.707 354 100 G+0.83 Unit k pF Vp Vp mVp mVp dB 1.8 -- -- 0 0c -- -- 500 1 -- VC-0.83 2 -- -- -- -- -- -- -- -- 10d VC 2.2 1 100 50 100 1 2 -- -- -- VC+0.83 V mA mV nF nF Vp Vp k k dB a. Min. value reached for a codec clock of 3MHz, typ. for 2MHz and max. for 100KHz b. 0dBm0 corresponds to 3.14dB below the input saturation level c. AC coupling is necessary in single-ended mode when the load resistor is not tied to Vref d. 10% MOTOROLA DSP56166 Technical Data Sheet 6 PRELIMINARY - 6/15/93 Analog I/O Figure 1. describes the recommended analog I/O and power supply configurations. The two analog inputs are electrically identical. When one is not used, it can be left floating. When used, an AC coupling capacitor is required. The value of the capacitor along with the input impedance of the pin determine the cut off frequency of a high pass filter. The input impedance of the MIC and AUX varies as a function of the modulator master clock. 78 k is a typical value at 2MHz. An AC capacitor of 1F defines a high pass filter pole of 2 Hz. A smaller capacitor value will move this pole higher in frequency. 5.6K Vrad Mic VddA INS bit MGS1-0 bits -6dB 1F 600 MUX 0.001F 600 1F 0.001F 15F + VssA 15F + VssA < 0.1F 50nF (MAX 1Vp when single ended on 0.5K) digital Vdd digital Vss MAX 2Vp 5.6K Vrad VssA Aux 6dB modulator Vrad 2.0V 10% (2/5 Vdd) Vrda 0.1F ( 1mA) 0.1F Vdiv 17dB 54K 36K Spkp 1K Spkm VC3-VC0 VddA VssA RC 2 POLE LPF 0.01F 220F + Single trace 15F +5V Single trace + 0.1F Analog Decoupling near DSP GND VssA Ext. GND Ext. Supply Analog I/O Figure 1. Recommended Analog I/O Configuration 7 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 Analog I/O Figure 2. shows three possible single-ended output configurations. Configuration (a) is highly recommended. For configuration (b) and (c), since the load resistor is tied to VssA, an AC coupling capacitor is required. Vref VddA + VssA 47K (a) (b) 47K Spkm NC Spkm 0 MOTOROLA DSP56166 Technical Data Sheet 8 PRELIMINARY - 6/15/93 A/D and D/A Performances (VddA = 5.0 Vdc +/- 10%, TJ = -40 to +125 C). The A/D and D/A performances of the codec section are given below. Characteristic Analog to Digital Section Signal to Noise plus Distortion Ratio (S/N+T) Level Min. tbd tbd tbd tbd tbd tbd tbd tbd Typ.a 65 60 50 20 60 55 45 15 Max. -- -- -- -- -- -- -- -- Unit dB dB dB dB dB dB dB dB 0dBm0b -10dBm0 -20dBm0 -50dBm0 Digital to Analog Section Signal to Noise plus Distortion Ratio (S/N+T) 0dB -10dB -20dB -50dB a. 0dB gain on the A/D and D/A; Codec clock at 2.048MHz with 128 decimation/interpolation ratio b. 0dBm0 corresponds to -3.14dB below the input saturation level 80 70 S/N S/N+T 60 50 dB 40 30 20 10 0 0 -2.86 -5.85 -8.84 -47.8 -11.85 -14.85 -17.85 -20.86 -23.86 -26.85 -29.89 -32.85 -35.84 -38.85 -41.85 -44.85 -50.81 -53.77 -56.76 59.76 -62.83 -65.67 -68.79 -71.91 -74.58 S in dB Analog I/O Figure 3. Example: S/N & S/N+T Performance for the A/D section 9 DSP56166 Technical Data Sheet MOTOROLA -77.91 PRELIMINARY - 6/15/93 Other On-Chip Codec Characteristics (VddA = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). The Analog I/O characteristics of this device are shown below. Characteristic Codec Master Clock Codec Sampling rate A/D section settling time D/A section settling time A/D section group delay D/A section group delay A/D to D/A Crosstalk D/A to A/D Crosstalk Idle noise at the D/A output Idle noise at the A/D digital output Min 0.1 78 -- -- -- -- -- -- -- -- Typ 2.048 16000 -- -- -- -- -- -- -- -- Max 3 46150 tbd tbd 0.2 0.2 tbd tbd tbd tbd Unit MHz Hz msec msec msec msec dB dBm0 Vrms dBm0 MOTOROLA DSP56166 Technical Data Sheet 10 PRELIMINARY - 6/15/93 DC Electrical Characteristics (VSS = 0 Vdc) (Vdd = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). The DC electrical characteristics of this device are shown below. Characteristic Input High Voltage Except EXTAL, RESET, MODA, MODB,MODC Input Low Voltage Except EXTAL, MODA, MODB, MODC Input High Voltage EXTAL DC coupled EXTAL AC coupled (see note 1) Input Low Voltage EXTAL DC coupled EXTAL AC coupled (see note 1) Input High Voltage RESET Symbol VIH VIL VIHC Min 2.0 -0.5 Typ -- -- Max Vdd 0.8 Un it V V V 70% of Vdd 1 VILC -0.5 -0.5 VIHR VIHM VILM Iin TSI VOHC VOH VOLC VOL 2.5 3.5 -0.5 -1 -10 Vdd -0.1 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Vdd Vdd V 20% of Vdd Vdd-1 Vdd Vdd 2.0 1 10 -- V V V uA uA V V V V Input High Voltage MODA , MODB, MODC Input Low Voltage MODA , MODB, MODC Input Leakage Current EXTAL, RESET, MODA, MODB, BR Three-State (Off-State) Input Current (@2.4 V/0.5 V) Output High Voltage Output High Voltage Output Low Voltage (IOH = -10 uA) (IOH = -0.4 mA) (IOL = 10 uA) -- 0.1 0.4 Output Low Voltage (IOL = 3.2 mA; R/W IOL = 1.6 mA; Open Drain HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA) Input Capacitance NOTES: (see Note 2) Cin -- 10 -- pF 1. When EXTAL is AC coupled, VIHC - VILC 1V must be true. 2. Input capacitance is periodically sampled and not 100% tested in production. 11 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 AC Electrical Characteristics (VSS = 0 Vdc) The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and MODC. These five pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. The DSP56166 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V respectively. AC Electrical Characteristics -- Clock Operation Timing The system clock to the DSP56166 must be externally supplied to EXTAL. 60MHz Num Characteristics Sym Min 1 2 3 4 5 6 7 8 Frequency of Operation (EXTAL) Instruction Cycle Time =2Tc Wait State =Tc =2T EXTAL Cycle Period EXTAL Rise Time (see Note 1) EXTAL Fall Time (see Note 1) EXTAL Width High (see Note 2, 3, 4) 48-52% duty cycle EXTAL Width Low (see Note 2, 3, 4) 48%-52% duty cycle Th Tl f Icyc WS Tc 0 33 16.6 16.6 -- -- 8 8 Max 60 3 3 MHz ns ns ns ns ns ns ns Unit Notes: 1. Rise and Fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is less than or equal to 20MHz. If the EXTAL input frequency is between 20MHz and 40MHz, Rise and Fall time should be 4 ns maximum. If the EXTAL input frequency is between 40MHz and 60MHz, Rise and Fall time should meet the specified values in the 40MHz column (3 ns maximum). 2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20MHz. If the EXTAL input frequency is between 20MHz and 40MHz, the duty cycle should be such that Th and Tl meet 12 ns minimum . If the EXTAL input frequency is between 40MHz and 60MHz, the duty cycle should be such that Th and Tl meet the specified values in the 60MHz column (8 ns minimum) . 3. T = Icyc / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty cycle of the external clock input. 4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and at Vdd/2 when not AC coupled. Th Tl VIHC 90% Midpoint 10% VILC 6 2 5 EXTAL 7 4 8 MOTOROLA DSP56166 Technical Data Sheet 12 PRELIMINARY - 6/15/93 Clock Figure 1. External Clock Timing AC Electrical Characteristics -- Other Clock and PLL Operation Timing Characteristics PLL Output frequency EXTAL Input Clock Amplitude b Min 10 1 Max Max Fosca Vdd Unit MHz Vpp a. Maximum DSP operating frequency. See Operating Conditions. b. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level range (VILC>20% of Vdd or VIHC<70% of Vdd). 10nF XFC1 0.01F 0.1F SXFC / 1 to / 16 VDDS GNDS PD3-PD0 / 20 to / 215 PLLE=1 Fosc PLLE=0 EXTAL 1000pF 100K ID3-ID0 PFD PLL LF / 1 to / 256 YD7-YD0 VCO PS=0 CS1-CS0 PS=1 CLKO /2 internal phase PH0 at Fosc Notes: 1. Must be a low leakage capacitor and must be located very close to the SXFC and VDDS pins. Clock Figure 2. Clocking Configurations 13 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Reset, Stop, Wait, Mode Select, and Interrupt Timing (Vdd = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles ws= Number of wait states programmed into external bus access using BCR (WS = 0 - 31) 60MHz Num Characteristics Min 10 RESET Assertion to Address, Data and control signals High Impedance Minimum Stabilization Duration(see Note 1 )OMR bit6=0 OMR bit6=1 Asynchronous RESET Deassertion to First External Address Output (see note 7) Synchronous Reset Setup Time from RESET Deassertion to Rising Edge of CLKO Synchronous Reset Delay Time from CLKO High to the First External Access (see note 7) Mode Select Setup Time Mode Select Hold Time Edge-Triggered Interrupt Request Width Delay from IRQA, IRQB, IRQC Assertion to External Data Memory Access Out Valid - Caused by First Interrupt Instruction Fetch - Caused by First Interrupt Instruction Execution Delay from IRQA, IRQB, IRQC Assertion to General Purpose -- Max 21 ns Unit 11 600KT 60T 16T -- -- 18T +15 cyc-2 ns ns ns 12 13 5 ns 14 16T +3 16T +16 ns 15 16 17 18 4.8 0.8 3.7 -- -- -- ns ns ns 11T+3 19T+3 22T -- -- -- ns ns ns 19 MOTOROLA DSP56166 Technical Data Sheet 14 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued) (Vdd = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). 60MHz Num Characteristics Min 21 Delay from General-Purpose Output Valid Caused by the Execution of the First Interrupt Instruction to IRQA, IRQB, IRQC Deassertion for Level Sensitive Fast Interrupts -- If 2nd Interrupt Instruction is: Single Cycle (see note 2) Two Cycles Synchronous setup time from IRQA, IRQB, IRQC assertion to Synchronous falling edge of CLKO (see note 5, 6) Falling Edge of CLKO to First Interrupt Vector Address Out Valid after Synchronous recovery from Wait State (see Note 3, 5) IRQA Width Assertion to Recover from STOP State(see note 4) Delay from IRQA Assertion to Fetch of first instruction (exiting STOP) OMR bit 6 = 0 (see note1,3) OMR bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting STOP) (see note1,3) OMR bit 6 = 0 OMR bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting STOP) (see note1, 3) OMR bit 6 = 0 OMR bit 6 = 1 Max Unit -- -- 0 cyc26 3cyc26 1 ns ns ns 22 23 27T+ 3 27T+ 16 ns 24 25 3.6 -- ns 524303T +3 47T+3 -- -- ns ns 28 524303T 47T -- -- ns ns 29 524303T +3 47T+3 -- -- ns ns Notes: 1. Circuit stabilization delay is required during reset when using an external clock in two cases: 1) after power-on reset, and 2) when recovering from Stop mode. 15 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 2. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 20 & 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edgetriggered mode is recommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode. 3. The interrupt instruction fetch is visible on the pins only in Mode 3. 4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover from the STOP state. This is not the minimum required so that the IRQA interrupt is accepted. 5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting WAIT 6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the WAIT state. 7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3. VIHR RESET 11 10 D0-D15, A0-A15,PS/DS R/W,BS,PEREN 12 First Fetch Interrupt Figure 1. Asynchronous Reset Timing CLKO 13 RESET A0-A15, PS/DS, BS, R/W,PEREN 14 Interrupt Figure 2. Synchronous Reset Timing VIHR RESET 15 16 VIHM MODA, MODB, MODC VILM VIH VIL IRQA, IRQB IRQC Interrupt Figure 3. Operating Mode Select Timing MOTOROLA DSP56166 Technical Data Sheet 16 PRELIMINARY - 6/15/93 IRQA, IRQB, IRQC 17 Interrupt Figure 4. External Interrupt Timing (Negative Edge-Triggered) A0-A15 PS/DS BS, R/W PEREN 18 IRQA IRQB, IRQC First Interrupt Instruction Execution 20 a) First Interrupt Instruction Execution General Purpose I/O 19 IRQA IRQB, IRQC b) General Purpose I/O 21 Interrupt Figure 5. External Level-Sensitive Fast Interrupt Timing 17 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 CLKO T0, T2 phi0 22 T1, T3 phi1 IRQA, IRQB, IRQC 23 A0-A15, PD/DS BS,R/W,PEREN First Interrupt Instruction Fetch Wait and Stop 1. Synchronous Interrupt from Wait State Timing IRQA 24 25 A0-A15, PD/DS BS,R/W,PEREN First Instruction Fetch Not IRQA Interrupt Vector Wait and Stop 2. Recovery from STOP State using Asynchronous Interrupt Timing IRQA 28 29 A0-A15, PD/DS BS,R/W,PEREN First IRQA Interrupt Instruction Fetch Wait and Stop 3. Recovery from Stop State Using IRQA Interrupt Service MOTOROLA DSP56166 Technical Data Sheet 18 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Wait and Stop Timings (Continued) 60MHz Num Characteristics Min 30 DR Asserted to CLK low (Setup Time for Synchronous Recovery from Wait State) CLK low to DSO (ACK) Valid (Enter Debug Mode) After Synchronous Recovery from Wait State Max Unit 8 cyc+8 ns 31 18cyc -- ns CLKO (output) T0, T2 T1, T3 33 DR (input) 30 DSO (output) 31 Wait and Stop 4. Recovery from WAIT State Using DR Pin-- Synchronous Timing 19 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 33 33 DR (input) 32 DSO (output) Wait and Stop 5. Recovery from WAIT/STOP State Using DR Pin-- Asynchronous Timing MOTOROLA DSP56166 Technical Data Sheet 20 PRELIMINARY - 6/15/93 AC Electrical Characteristics Capacitance Derating --External Bus Synchronous Timing VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load. The DSP56166 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS/DS, RD, WR, R/W, BS, PEREN) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. When an internal memory access follows an external memory access, the PS/DS, R/W, RD, WR, BS and PEREN strobes remain deasserted and A0-A15 do not change from their previous state. 21 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 60MHz Num Characteristic Min 34 35 CLK in (EXTAL) High to CLKO High CLKO High to a. A0-A15 Valid b. PS/DS, PEREN Assertion, R/W Valid c. BS Assertion d. RD Assertion BS Width Deassertion CLKO High to WR Assertion Low 14.6 5.8 8.7 8.7 8.3 -- T+ 6.0 Max ns ns ns ns ns ns ns Unit 36 37 38 39 40 41 42 43 44 45 46 47 CLKO High to BS Deassertion a.TA Assertion to CLKO High (Setup) b.TA Deassertion to CLKO High (Setup) a. CLKO High to TA Assertion (Hold) b. CLKO High to TA Deassertion (Hold) CLKO High to D0-D15 Out Valid CLKO High to D0-D15 Out Invalid (Hold) D0-D15 In Valid to CLKO Low (Setup) CLKO Low to D0-D15 In Invalid (Hold) CLKO Low to a. WR Deassertion b. RD Deassertion a. WR Hold Time from CLKO Low b. RD Hold Time from CLKO Low CLKO High to D0-D15 Three-state CLKO High to D0-D15 Out Active CLKO High to a. A0-A15 Invalid b. PS/DS, PEREN ,R/W Invalid 1.5 5.9 8.3 -- -- -- -- 8.8 1.6 2.5 0.1 -- -- 1.6 0.5 -- -- -- 4.8 4.0 -- -- TBD TBD 1.1 2.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 48 49 50 51 MOTOROLA DSP56166 Technical Data Sheet 22 PRELIMINARY - 6/15/93 T0 EXTAL (Input) CLKO (Output) A0-A15, PS/DS,R/W PEREN Note 1 BS (Output) 37 WR (Output) 35 RD (Output) 34 35 T1 T2 T3 T0 T1 T2 51 35 40 36 47 48 47 48 42 TA (Input) 43 D0-D15 (Output) 50 D0-D15 (Input) 45 41 41 44 Data Out 49 46 Data In External Bus Figure 1. External Bus Synchronous Timing -- No Wait States Note 1: During Read-Modify-Write instructions and internal instructions, the address lines do not change state 23 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 T0 EXTAL (Input) CLKO (Output) A0-A15, PS/DS,R/W PEREN (Outputs) BS (Output) 37 WR (Output) 34 35 T1 T2 Tw T2 Tw T2 T3 T0 51 35 40 36 47 48 35 RD (Output) 47 48 41 42 41 42 TA (Input) 44 43 D0-D15 (Output) 50 46 45 D0-D15 (Input) Data In Data Out 49 External Bus Figure 2. External Bus Synchronous Timing - Two Wait States MOTOROLA DSP56166 Technical Data Sheet 24 PRELIMINARY - 6/15/93 AC Electrical Characteristics External Bus Asynchronous Timing VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load. cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States, Determined by BCR Register (WS = 0 to 31) WT = WS*cyc=2T*WS 60MHz Num Characteristic Min 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 WR and RD Deassertion High to BS Assertion Low (2 Successive Bus Cycles) Address Valid to WR Assertion WR Width Assertion WS=0 WS>0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD -- -- Max TBD TBD -- -- -- TBD TBD -- -- -- -- -- -- -- TBD TBD -- -- TBD TBD TBD TBD TBD -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit WR Deassertion to R/W, Address Invalid WR Assertion to D0-D15 Out Valid Data Out Hold Time from WR Deassertion Data Out Set up Time to WR Deassertion WS=0 WS>0 RD Deassertion to Adress not valid Address valid to RD Deassertion Input data hold to RD Deassertion RD Assertion width WS=0 WS>0 Address valid to input data valid WS=0 WS>0 Address valid to RD Assertion RD Assertion to input data valid WS=0 WS>0 WR Deassertion to RD Assertion RD Deassertion to RD Assertion WR Deassertion to WR Assertion RD Deassertion toWR Assertion 25 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 A0-A15, PS/DS, R/W PEREN 60 BS 59 64 RD 53 68 WR 56 58 D0-D15 Data Out 57 63 54 55 62 67 52 52 66 65 69 61 Data In Note: 1. During Read-Modify-Write instructions and internal instructions, the address lines do not change state. External Bus Figure 3. External Bus Asynchronous Timing MOTOROLA DSP56166 Technical Data Sheet 26 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Bus Arbitration Timing -- Slave Mode VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load. cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles WS = Number of Wait States for X or P external memory , Determined by BCR or BCR2 Registers (WS = 0 to 31) WT = WS*cyc=2T*WS Wx = Number of Wait States for X external memory, Determined by BCR or BCR2 Registers (WS = 0 to 31) Wp = Number of Wait States for P external memory, Determined by BCR Register (WS = 0 to 31) 60 MHz Num 70 71 Characteristics Min BR Input to CLKO low setup time Delay from BR Input Assertion to BG Output Assertion (See note 1) (See note 2) (See note 3) (See note 4) (See note 5) 2.8 TBD TBD TBD TBD TBD 7.2 TBD TBD TBD TBD TBD TBD -- -- -- -- -- -- Unit Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TBD TBD TBD TBD 2.0 TBD 8.5 TBD 8.5 ns ns ns ns ns ns ns ns ns 72 73 CLKO high to BG Output Assertion BG Output Deassertion duration (See note 1) for two consecutive BR (See note 2) (See note 3) (See note 4) (See note 5) (See note 7) CLKO High to Control Bus high impedance CLKO High to BB Output Deassertion CLKO High to BB Output (Three-state) BR Input Deassertion to BG Output Deassertion CLKO High to BG Deassertion CLKO High to BB Output Active CLKO High to BB Output Assertion CLKO High to Address and Control Bus Active CLKO High to Address and Control Bus Valid (See note 1) (See note 5) (See note 7) 10.3 74 75 76 77 TBD 78 79 80 81 82 27 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 60 MHz Num 83 Characteristics Min BR Assertion to BB Deassertion (See note 1) (See note 2) (See note 3) (See note 4) (See note 5) (See note 1) (See note 2) (See note 3) (See note 4) (See note 5) Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns ns Unit 84 BR Assertion to Addr/Data/Control Three-state NOTES: 1. With no external access from the DSP56166 2. During external read or write access 3. During external read-modify-write access 4. During STOP mode -- external bus is released and BG is always low 5. During WAIT mode 7. With external accesses pending by the DSP56166 8. Slave mode, when bus is still busy after bus request has been deasserted MOTOROLA DSP56166 Technical Data Sheet 28 PRELIMINARY - 6/15/93 CLKO (Output) 70 BR (Input) 71 72 BG (Output) 73 75 83 76 84 BB (I/O) A0-A15, PS/DS R/W PEREN 84 D0-D15 74 74 External Bus Figure 4. Bus Arbitration Timing -- Slave Mode -- Bus Release. 29 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 CLKO (Output) 70 BR (Input) 77 78 BG (Output) BB (I/O) 79 80 82 A0-A15, PS/DS R/W PEREN 81 External Bus Figure 5. Bus Arbitration Timing -- Slave Mode -- Bus Acquisition. MOTOROLA DSP56166 Technical Data Sheet 30 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Bus Arbitration Timing -- Master Mode VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load. 60MHz Num 85 86 87 88 89 90 91 Characteristic Min CLKO high to BR Output Valid BG Input Valid to CLKO Low (Setup) CLKO Low to BG Input Deassertion (Hold) BB Input Deassertion to CLKO Low (Setup) CLKO Low to BB Input Deassertion (Hold) CLKO High to BB Output Assertion CLKO Low to BG Input Assertion (See note 1) (See note 2) BG Deassertion to BB Deassertion (See note 1) (See note 2) (See note 3) (See note 4) (See note 5) (See note 1) (See note 2) (See note 3) (See note 4) (See note 5) TBD TBD 1.7 TBD 1.5 TBD Max 7.3 -- -- -- -- 8.0 -- -- TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 92 93 BG Deassertion to Addr/Data/Control Three-state NOTES: 1. With no external access from the DSP56166 2. During external read or write access 3. During external read-modify-write access 4. During STOP mode -- external bus is released and BG is always low 5. During WAIT mode 31 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 CLKO (Output) 85 BR (Output) 87 BG (Input) 86 88 BB (I/O) 89 Three-state 90 A0-A15, PS/DS R/W PEREN 82 81 External Bus Figure 6. Bus Arbitration Timing -- Master Mode -- Bus Acquisition. MOTOROLA DSP56166 Technical Data Sheet 32 PRELIMINARY - 6/15/93 CLKO (Output) 85 BR (Output) 86 BG (Input) 91 75 92 BB (I/O) Output 76 A0-A15, D0-D15, PS/DS, BS, R/W, RD, WR, PEREN 93 74 External Bus Figure 7. Bus Arbitration Timing -- Master Mode -- Bus Release. 33 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 HOST PORT USAGE CONSIDERATIONS Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host port. The considerations for proper operation are discussed below. Host Programmer Considerations 1. Unsynchronized Reading of Receive Byte Registers When reading receive byte registers, RXH or RXL, the Host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This assures that the data in the receive byte registers will be stable. 2. Overwriting Transmit Byte Registers The Host programmer should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. 3. Synchronization of Status Bits from DSP to Host HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF (refer to DSP56166 User's Manual, I/O Interface section, Host/DMA Interface Programming Model for descriptions of these status bits) status bits are set or cleared from inside the DSP and read by the Host processor. The Host can read these status bits very quickly without regard to the clock rate used by the DSP, but the possibility exists that the state of the bit could be changing during the read operation. This is generally not a system problem, since the bit will be read correctly in the next pass of any Host polling routine. However, if the Host asserts the HEN for more than timing number 101 (T101), with a minimum cycle time of timing number 103 (T103), then the status is guaranteed to be stable A potential problem exists when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the Host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the Host could read the wrong combination. Solution: a. Read the bits twice and check for consensus. b. Assert HEN access for T101a so that status bit transitions are stabilized. 4. Overwriting the Host Vector The Host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector. 5. Cancelling a Pending Host Command Exception The Host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is recognized by the DSP. Because the Host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the Host exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time the HC bit is cleared. DSP Programmer Considerations 1. Reading HF0 and HF1 as an Encoded Pair DMA, HF1, HF0, and HCP, HTDE, and HRDF (refer to DSP56166User's Manual, I/O Interface section, Host/DMA Interface Programming Model for descriptions of these status bits) status bits are set or cleared by the Host processor side of the interface. These bits are individually synchronized to the DSP clock. A potential problem exists when reading status bits HF1 and HF2 as an encoded pair, i.e., the four combinations 00, 01, 10, and 11 each have significance. A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the bits twice for consensus. MOTOROLA DSP56166 Technical Data Sheet 34 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Host I/O Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load, see Host Figures 1 through 6) T = Icyc / 4 cyc=Clock cycle =1/2 instruction cycle= 2 T cycle tHSDL = Host Synchronization Delay Time tsuh : Host processor data setup time Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications 60MHz Num Characteristic Min 100 101 Host Synchronous Delay (see Note 1) HEN/HACK Assertion Width a.CVR,ICR, ISR Read (see Note 2,4) b.Read c.Write HEN/HACK Deassertion Width (see Note 2) Minimum Cycle Time Between Two HEN Assertion for Consecutive CVR, ICR, ISR reads Host Data Input Setup Time Before HEN/HACK Deassertion Host Data Input Hold Time After HEN/HACK Deassertion HEN/HACK Assertion to Output Data Active from High Impedance HEN/HACK Assertion to Output Data Valid HEN/HACK Deassertion to Output Data High Impedance Output Data Hold Time After HEN/ HACK Deassertion T Max 3T ns Unit 2T+ 30 16+tsuh 8.0 27 4T+ 30 -- -- -- -- -- ns 102 103 ns ns 104 105 106 107 108 109 3 9 0 -- -- 5 -- -- -- 24 17 -- ns ns ns ns ns ns 35 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Host I/O Timing (Continued) 60MHz Num Characteristic Min 110 111 112 113 114 115 116 117 HR/W Low Setup Time Before HEN Assertion HR/W Low Hold Time After HEN Deassertion HR/W High Setup Time to HEN Assertion HR/W High Hold Time After HEN/HACK Deassertion HA0-HA2 Setup Time Before HEN Assertion HA0-HA2 Hold Time After HEN Deassertion DMA HACK Assertion to HREQ Deassertion(see Note 3) DMA HACK Deassertion to HREQ Assertion(see Note 3) for DMA RXL Read for DMA TXL Write for All Other Cases 118 119 120 Delay from HEN Deassertion to HREQ Assertion for RXL Read (see Note 3) Delay from HEN Deassertion to HREQ Assertion for TXL Write (see Note 3) Delay from HEN Assertion to HREQ Deassertion for RXL Read, TXL Write ( see Note 3) 4 4 4 3 0 6 4 Max -- -- -- -- -- -- 2T+ 35 ns ns ns ns ns ns ns Unit tHSDL +3T+4 tHSDL +2T+4 4 tHSDL +3T+4 tHSDL +2T+4 13.7 -- ns ns -- -- -- -- 2T+ 16.4 ns ns ns ns NOTES: 1. "Host synchronization delay (tHSDL)" is the time period required for the DSP56166 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the internal clock. 2. See HOST PORT USAGE CONSIDERATIONS. 3. HREQ is pulled up by 1k. 4. Only if two consecutive reads from one of these registers are executed. MOTOROLA DSP56166 Technical Data Sheet 36 PRELIMINARY - 6/15/93 EXTERNAL 100 INTERNAL 100 Host Figure 1. Host Synchronization Delay HREQ (OUTPUT) 103 101 HACK (INPUT) 112 HR/W (INPUT) 113 102 107 106 H0-H7 (OUTPUT) Data 109 Valid 108 Host Figure 2. Host Interrupt Vector Register (IVR) Read 37 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 HREQ (OUTPUT) 103 HEN (INPUT) RXH Read 101 114 HA2-HA0 (INPUT) Address Valid 112 HR/W (INPUT) 107 106 H0-H7 (OUTPUT) Data Valid 120 118 RXL Read 102 115 Address Valid 113 108 109 Data Valid Host Figure 3. Host Read Cycle (Non-DMA Mode) HREQ (OUTPUT) 103 HEN (INPUT) TXH Write 101 114 HA2-HA0 (INPUT) Address Valid 110 HR/W (INPUT) 104 H0-H7 (INPUT) Data Valid 120 119 TXL Write 102 115 Address Valid 111 105 Data Valid Host Figure 4. Host Write Cycle (Non-DMA Mode) MOTOROLA DSP56166 Technical Data Sheet 38 PRELIMINARY - 6/15/93 HREQ (OUTPUT) 116 101 102 117 HACK (INPUT) 107 106 H0-H7 (OUTPUT) RXH Read RXL Read 108 109 Data Valid Data Valid Host Figure 5. Host DMA Read Cycle HREQ (OUTPUT) 116 101 HACK (INPUT) 104 105 H0-H7 (INPUT) Data Valid Data Valid TXH Write 102 TXL Write 117 Host Figure 6. Host DMA Write Cycle 39 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 AC Electrical Characteristics -- RSSI Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 to + 125 C, CL = 50 pF + 1 TTL Load, see RSSI Figure 1 and 2) T = Icyc / 4 SCK Pin = Serial Clock SFS Pin = Transmit/Receive Frame Sync i ck = Internal Clock and Frame Sync x ck = External Clock and Frame Sync bl = bit length wl = word length NOTE: All the timings for the RSSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a noninverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK and/or the frame sync SFS in the tables and in the figures. 60MHz Num 130 131 132 133 134 135 136 137 138 139 Characteristic Min SCK Clock Cycle (see Note 1) SCK Clock High Period SCK Clock Low Period SCK Clock Rise/Fall Time SCK Rising Edge to SFS In (bl) High SCK Rising Edge to SFS In (bl) Low SCK Rising Edge to SFS In (wl) High SCK Rising Edge to SFS In (wl) Low Data In Setup Time Before SCK Falling Edge Data In Hold Time After SCK Falling Edge TBD TBD TBD -- -- -- -- -- TBD TBD Case Max -- -- -- TBD TBD TBD TBD TBD -- -- i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck Unit ns ns ns ns ns ns ns ns ns ns MOTOROLA DSP56166 Technical Data Sheet 40 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- RSSI Timing (Continued) 60MHz Num 140 141 142 143 144 145 146 Characteristic Min SCK Rising Edge to SFS Out (bl) High SCK Rising Edge to SFS Out (wl) High SCK Rising Edge to SFS Out Low SCK Rising Edge to Data Out Enable from High Impedance SCK Rising Edge to Data Out Valid SCK Rising Edge to Data Out Invalid SCK Rising Edge to Data Out High Impedance -- -- -- -- -- -- -- Case Max TBD TBD TBD TBD TBD TBD TBD i ck i ck i ck i ck i ck i ck i ck Unit ns ns ns ns ns ns ns NOTES: 1. For internal clock, Serial Clock Cycle is defined by Icyc and RSSI control register. 41 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 130 131 SCK Continuous (Output) SCK Gated (Output) 133 132 134 135 SFS(Bit Early) (Input) 136 137 134 135 SFS (Word Early) (Input) SFS(Bit ) (Input) 136 137 SFS (Word ) (Input) 143 STD (Output) 144 145 SRD (Input) 138 139 142 146 140 SFS(Bit Early) (Output) 141 142 140 142 SFS (Word Early) (Output) SFS(Bit ) (Output) 141 142 SFS (Word ) (Output) RSSI Figure 1. RSSI Internal ClockTiming MOTOROLA DSP56166 Technical Data Sheet 42 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- RSSI Timing (Continued) 60MHz Num 150 151 152 153 154 155 156 157 158 159 Characteristic Min SCK Clock Cycle (see Note 1) SCK Clock High Period SCK Clock Low Period SCK Clock Rise/Fall Time SCK Rising Edge to SFS Out (bl) High SCK Rising Edge to SFS Out (bl) Low SCK Rising Edge to SFS Out (wl) High SCK Rising Edge to SFS Out (wl) Low Data In Setup Time Before SCK Falling Edge Data In Hold Time After SCK Falling Edge SCK Rising Edge to SFS In (bl) High SCK Rising Edge to SFS In (bl) Low SCK Rising Edge to SFS In (wl) High TBD TBD TBD -- -- -- -- -- TBD TBD -- -- -- Case Max -- -- -- TBD TBD TBD TBD TBD -- -- TBD TBD TBD x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 160 161 162 163 SCK Rising Edge to Data Out Enable from High Impedance SCK Rising Edge to Data Out Valid SCK Rising Edge to Data Out Invalid SCK Rising Edge to Data Out High Impedance -- TBD 164 165 166 -- -- -- TBD TBD TBD x ck ns x ck ns x ck ns 43 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 150 151 SCK Continuous (Input) SCK Gated (Input) 153 152 154 155 SFS(Bit Early) (Output) 156 157 154 155 SFS (Word Early) (Output) SFS(Bit ) (Output) 156 157 SFS (Word ) (Output) 163 STD (Output) 164 165 SRD (Input) 158 159 162 166 160 SFS(Bit Early) (Input) 161 162 160 162 SFS (Word Early) (Input) SFS(Bit ) (Input) 161 162 SFS (Word ) (Input) RSSI Figure 2. RSSI External ClockTiming MOTOROLA DSP56166 Technical Data Sheet 44 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- Timer Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). 60MHz Num 170 171 172 173 174 175 Characteristic Min TIN Valid to CLKO low (Setup time) CLKO Low to TIN Invalid (Hold time) CLKO High to TOUT Asserted CLKO High to TOUT Deasserted Tin Period Tin High/Low Period 6 0 3.5 5.1 8T 4T Max -- -- 14 20.7 -- -- ns ns ns ns ns ns Unit CLKO (Output) 170 TIN (Input) 172 171 TOUT (Output) 173 Timer Figure 1. Timer Timing 45 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 AC Electrical Characteristics -- OnCE Timing VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). 60 MHz Num 180 181 182 183 184 185 186 187 188 Characteristic Min DSCK High to DSO Valid DSI Valid to DSCK Low (Setup) DSCK Low to DSI Invalid (Hold) DSCK High (See note 1) DSCK Low (See note 1) DSCK Cycle Time (See note 1) CLKO High to OS0-OS1 Valid CLKO High to OS0-OS1 Invalid Last DSCK High to OS0-OS1(See note 2) Last DSCK High to ACK Active (data)(See note 2) Last DSCK High to ACK Active (command)(See note 2) DSO (ACK) Asserted to OS0-OS1 Three-state DSO (ACK) Asserted to First DSCK High DSO (ACK) Width Asserted: a. when entering debug mode b. when acknowledging command/data transfer Last DSCK Low of Read Register to First DSCK High of Next Command DSCK High to DSO Invalid (See note 2) DR asserted to DSO (ACK) Asserted -- 10T+Td+14.5 10T+Td+13.5 21T+Td+13.5 -- 3Tc 8T+1.1 9T+1.1 6Tc 10.9 11T+19.5 -- 1 0.9 2Tc 2Tc 4Tc Unit Max 27.6 -- -- -- -- -- 14.5 -- -- -- TBD -- 8T+4.1 9T+4.1 -- -- -- ns ns ns ns ns ns ns ns ns 189 190 191 ns ns ns ns ns ns ns 192 193 194 NOTES: 1. 45%-55% duty cycle 2. Td=DSCK High (183) MOTOROLA DSP56166 Technical Data Sheet 46 PRELIMINARY - 6/15/93 183 DSCK (Input) 184 185 OnCE Figure 1. OnCE Serial Clock Timing DR (Input) 194 DSO (Output) ACK OnCE Figure 2. OnCE Acknowledge Timing DSCK (Input) 180 DSO (Output) (Last) Note 1 193 (OS1) (ACK) DSI (Input) 181 182 Note 1: Three-state, external pull-down resistor 188 (OS0) OnCE Figure 3. OnCE Data I/O To Status Timing 47 DSP56166 Technical Data Sheet MOTOROLA PRELIMINARY - 6/15/93 190 OS1 (Output) (Note 1) DSO (Output) 180 191 (DSCK input) OS0 (Output) (DSO Output) 189 181 (DSI input) 182 Note 1: Three-state, external pull-down resistor OnCE Figure 4. OnCE Data I/O To Status Timing CLKO (Output) OS0-1 (Output) 187 186 OnCE Figure 5. OnCE CLK To Status Timing DSCK (Input) (Read Register) 192 (Next Command) OnCE Figure 6. OnCE DSCK Next Command After Read Register Timing MOTOROLA DSP56166 Technical Data Sheet 48 PRELIMINARY - 6/15/93 AC Electrical Characteristics -- General Purpose I/O (GPIO) Timing (VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125 C, CL = 50 pF + 1 TTL Load). 60 MHz Num 201 202 203 204 Characteristic Min CLKO Edge to GPIO Out Valid (GPIO Out Delay Time) CLKO Edge to GPIO Out Not Valid (GPIO Out Hold Time) GPIO In Valid to CLKO Edge (GPIO In Set-upTime) CLKO Edge to GPIO In Not Valid (GPIO In Hold Time) TBD Unit Max TBD ns ns ns ns TBD TBD TBD TBD TBD TBD CLKO (Output) 201 202 GPIO (Output) 203 GPIO (Input) VALID 204 GPIO Figure 1. GPIO Timing 49 DSP56166 Technical Data Sheet MOTOROLA Advance Information MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by DSP56166ROM/D DSP56166ROM Ceramic Quad Flat Pack (CQFP) Available in a 112 pin, small footprint, surface mount package. 16-bit General Purpose Digital Signal Processor The DSP56166ROM is the second member of Motorola's DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166ROM has a built-in codec and phase locked loop (PLL). This MPU-style DSP also contains, memories, peripherals, and provides a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCETM) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly simplified by using the OnCE. The DSP56166 ROM based part contains a 12K ROM (8K x 16 program ROM and 4K x 16 data ROM). The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166ROM. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools of the DSP56100, DSP56000, and DSP96000 families are so similar that learning to design and program one greatly reduces the time needed to learn the others. DSP56166ROM Feature List DSP56100 Family Features * Up to 30 Million Instructions per Second (MIPS) at 60 MHz.- 33.3 ns Instruction cycle * Single-cycle 16 x 16-bit parallel Multiply-Accumulate * 2 x 40-bit accumulators with extension byte * Fractional and integer arithmetic with support for multiprecision arithmetic * Highly parallel instruction set with unique DSP addressing modes * Nested hardware DO loops including infinite loops and DO zero loop * Two instruction LMS adaptive filter loop * Fast auto-return interrupts * Three external interrupt request pins * Three 16-bit internal data and three 16-bit internal address buses * Individual programmable wait states on the external bus for program, data, and peripheral memory spaces * Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin * On-chip memory-mapped peripheral registers * Low Power Wait and Stop modes * On-Chip Emulation (OnCE) for unobtrusive, processor speed independent debugging * Operating frequency down to DC * 5V single power supply * Low power (HCMOS) DSP56166ROM On-chip Resources * * * * * * * 4K x 16 on-chip data RAM 4K x 16 on-chip data ROM 256 x 16 on-chip program RAM 8K x 16 on-chip program ROM One external 16-bit address bus One external 16-bit data bus On-chip voice band codec (A/D-D/A) - Internal voltage reference (2/5 of positive power supply) - No off-chip components required 25 general purpose I/O pins On-chip, programmable PLL Byte-wide Host Interface with DMA support Two independent reduced synchronous serial interfaces * One 16-bit timer * 112 pin quad flat pack packaging * * * * Operational Differences Of The ROM Based Part From The RAM Based Part * XROM can only be accessed during a single read or the first read of a dual parallel read instruction (see note on back. * No bootstrap ROM * Reset mode 1 vectors to P:$0100 * PROM area P:$2080 -- P:$20FF is reserved and should not be programmed or accessed by the user This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA (c) MOTOROLA INC., 1993 July 14, 1993 OnCE is a trademark of Motorola, Inc. All product and brand names appearing herein are trademarks or registered trademarks of their respective holders. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typical", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and b are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, United Kingdom. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. XAB1 XAB2 PORT B OR HOST ADDRESS GENERATION UNIT PAB EXTERNAL ADDRESS BUS SWITCH ADDRESS 16 15 7+10 ON-CHIP PERIPHERALS HOST, RSSI0, RSSI1, TIMER GPI/O, CODEC PROGRAM MEMORY PRAM PROM 256 x 16 8K x 16 DATA MEMORY DATA RAM 4Kx16 DATA ROM 4Kx16 BUS CONTROL PORT A 10 CODEC, PORT C AND/OR RSSI0, RSSI1, TIMER XDB INTERNAL DATA BUS SWITCH AND BIT MANIPULATION UNIT PDB GDB EXTERNAL DATA BUS SWITCH 16 DATA EXTAL SXFC CLKO CLOCK AND PLL PROGRAM CONTROL UNIT PROGRAM ADDRESS GENERATOR PROGRAM DECODE CONTROLLER PROGRAM INTERRUPT CONTROLLER DATA ALU 16x16+40 - 40-BIT MAC TWO 40-BIT ACCUMULATORS OnCE 4 RESET MODA/IRQA MODB/IRQB MODC/IRQC 16 BITS DSP56166ROM Block Diagram In the USA: For technical assistance call: DSP Applications Helpline (512) 891-3230 For availability and literature call your local Motorola Sales Office or Authorized Distributor. For free application software and information call the Dr. BuB electronic bulletin board: 9600/4800/2400/1200/300 baud (512) 891-3771 (8 data bits, no parity, 1 stop) In Europe, Japan and Asia Pacific Contact your regional sales office or Motorola distributor. Note: Since the on-chip XROM is only connected to the XAB1 address bus (see the block diagram above), the data located in this ROM is only accessible by the first read of a single read instruction or the first read of a dual parallel read instruction. Therefore, during development using the RAM based part, the data to be mapped in the on-chip XROM on the ROM based part should not be accessed with a second read during a dual parallel read instruction. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbor Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MOTOROLA Corrections to the DSP56166 Data Sheet Dated 6/15/93 1. Remove the entry for the BIAS pin (page 9 of the 6/15/93 data sheet) |
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